Based on kernel version 6.11. Page generated on 2024-09-24 08:21 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek Functional Clock Controller for MT8192 maintainers: - Chun-Jie Chen <chun-jie.chen@mediatek.com> description: The Mediatek functional clock controller provides various clocks on MT8192. properties: compatible: items: - enum: - mediatek,mt8192-scp_adsp - mediatek,mt8192-imp_iic_wrap_c - mediatek,mt8192-imp_iic_wrap_e - mediatek,mt8192-imp_iic_wrap_s - mediatek,mt8192-imp_iic_wrap_ws - mediatek,mt8192-imp_iic_wrap_w - mediatek,mt8192-imp_iic_wrap_n - mediatek,mt8192-msdc_top - mediatek,mt8192-mfgcfg - mediatek,mt8192-imgsys - mediatek,mt8192-imgsys2 - mediatek,mt8192-vdecsys_soc - mediatek,mt8192-vdecsys - mediatek,mt8192-vencsys - mediatek,mt8192-camsys - mediatek,mt8192-camsys_rawa - mediatek,mt8192-camsys_rawb - mediatek,mt8192-camsys_rawc - mediatek,mt8192-ipesys - mediatek,mt8192-mdpsys reg: maxItems: 1 '#clock-cells': const: 1 required: - compatible - reg additionalProperties: false examples: - | scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0x10720000 0x1000>; #clock-cells = <1>; }; - | imp_iic_wrap_c: clock-controller@11007000 { compatible = "mediatek,mt8192-imp_iic_wrap_c"; reg = <0x11007000 0x1000>; #clock-cells = <1>; }; - | imp_iic_wrap_e: clock-controller@11cb1000 { compatible = "mediatek,mt8192-imp_iic_wrap_e"; reg = <0x11cb1000 0x1000>; #clock-cells = <1>; }; - | imp_iic_wrap_s: clock-controller@11d03000 { compatible = "mediatek,mt8192-imp_iic_wrap_s"; reg = <0x11d03000 0x1000>; #clock-cells = <1>; }; - | imp_iic_wrap_ws: clock-controller@11d23000 { compatible = "mediatek,mt8192-imp_iic_wrap_ws"; reg = <0x11d23000 0x1000>; #clock-cells = <1>; }; - | imp_iic_wrap_w: clock-controller@11e01000 { compatible = "mediatek,mt8192-imp_iic_wrap_w"; reg = <0x11e01000 0x1000>; #clock-cells = <1>; }; - | imp_iic_wrap_n: clock-controller@11f02000 { compatible = "mediatek,mt8192-imp_iic_wrap_n"; reg = <0x11f02000 0x1000>; #clock-cells = <1>; }; - | msdc_top: clock-controller@11f10000 { compatible = "mediatek,mt8192-msdc_top"; reg = <0x11f10000 0x1000>; #clock-cells = <1>; }; - | mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8192-mfgcfg"; reg = <0x13fbf000 0x1000>; #clock-cells = <1>; }; - | imgsys: clock-controller@15020000 { compatible = "mediatek,mt8192-imgsys"; reg = <0x15020000 0x1000>; #clock-cells = <1>; }; - | imgsys2: clock-controller@15820000 { compatible = "mediatek,mt8192-imgsys2"; reg = <0x15820000 0x1000>; #clock-cells = <1>; }; - | vdecsys_soc: clock-controller@1600f000 { compatible = "mediatek,mt8192-vdecsys_soc"; reg = <0x1600f000 0x1000>; #clock-cells = <1>; }; - | vdecsys: clock-controller@1602f000 { compatible = "mediatek,mt8192-vdecsys"; reg = <0x1602f000 0x1000>; #clock-cells = <1>; }; - | vencsys: clock-controller@17000000 { compatible = "mediatek,mt8192-vencsys"; reg = <0x17000000 0x1000>; #clock-cells = <1>; }; - | camsys: clock-controller@1a000000 { compatible = "mediatek,mt8192-camsys"; reg = <0x1a000000 0x1000>; #clock-cells = <1>; }; - | camsys_rawa: clock-controller@1a04f000 { compatible = "mediatek,mt8192-camsys_rawa"; reg = <0x1a04f000 0x1000>; #clock-cells = <1>; }; - | camsys_rawb: clock-controller@1a06f000 { compatible = "mediatek,mt8192-camsys_rawb"; reg = <0x1a06f000 0x1000>; #clock-cells = <1>; }; - | camsys_rawc: clock-controller@1a08f000 { compatible = "mediatek,mt8192-camsys_rawc"; reg = <0x1a08f000 0x1000>; #clock-cells = <1>; }; - | ipesys: clock-controller@1b000000 { compatible = "mediatek,mt8192-ipesys"; reg = <0x1b000000 0x1000>; #clock-cells = <1>; }; - | mdpsys: clock-controller@1f000000 { compatible = "mediatek,mt8192-mdpsys"; reg = <0x1f000000 0x1000>; #clock-cells = <1>; }; |