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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 | Mediatek IPU controller ============================ The Mediatek ipu controller provides various clocks to the system. Required Properties: - compatible: Should be one of: - "mediatek,mt8183-ipu_conn", "syscon" - "mediatek,mt8183-ipu_adl", "syscon" - "mediatek,mt8183-ipu_core0", "syscon" - "mediatek,mt8183-ipu_core1", "syscon" - #clock-cells: Must be 1 The ipu controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Example: ipu_conn: syscon@19000000 { compatible = "mediatek,mt8183-ipu_conn", "syscon"; reg = <0 0x19000000 0 0x1000>; #clock-cells = <1>; }; ipu_adl: syscon@19010000 { compatible = "mediatek,mt8183-ipu_adl", "syscon"; reg = <0 0x19010000 0 0x1000>; #clock-cells = <1>; }; ipu_core0: syscon@19180000 { compatible = "mediatek,mt8183-ipu_core0", "syscon"; reg = <0 0x19180000 0 0x1000>; #clock-cells = <1>; }; ipu_core1: syscon@19280000 { compatible = "mediatek,mt8183-ipu_core1", "syscon"; reg = <0 0x19280000 0 0x1000>; #clock-cells = <1>; }; |