Based on kernel version 6.10
. Page generated on 2024-07-16 09:00 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7) maintainers: - Stephen Boyd <sboyd@kernel.org> description: | The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI controller with wrapping arbitration logic to allow for multiple on-chip devices to control up to 2 SPMI separate buses. The PMIC Arbiter can also act as an interrupt controller, providing interrupts to slave devices. properties: compatible: const: qcom,x1e80100-spmi-pmic-arb reg: items: - description: core registers - description: tx-channel per virtual slave registers - description: rx-channel (called observer) per virtual slave registers reg-names: items: - const: core - const: chnls - const: obsrvr ranges: true '#address-cells': const: 2 '#size-cells': const: 2 qcom,ee: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 5 description: > indicates the active Execution Environment identifier qcom,channel: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 5 description: > which of the PMIC Arb provided channels to use for accesses patternProperties: "^spmi@[a-f0-9]+$": type: object $ref: /schemas/spmi/spmi.yaml unevaluatedProperties: false properties: reg: items: - description: configuration registers - description: interrupt controller registers reg-names: items: - const: cnfg - const: intr interrupts: maxItems: 1 interrupt-names: const: periph_irq interrupt-controller: true '#interrupt-cells': const: 4 description: | cell 1: slave ID for the requested interrupt (0-15) cell 2: peripheral ID for requested interrupt (0-255) cell 3: the requested peripheral interrupt (0-7) cell 4: interrupt flags indicating level-sense information, as defined in dt-bindings/interrupt-controller/irq.h required: - compatible - reg-names - qcom,ee - qcom,channel additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> soc { #address-cells = <2>; #size-cells = <2>; spmi: arbiter@c400000 { compatible = "qcom,x1e80100-spmi-pmic-arb"; reg = <0 0x0c400000 0 0x3000>, <0 0x0c500000 0 0x4000000>, <0 0x0c440000 0 0x80000>; reg-names = "core", "chnls", "obsrvr"; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; #size-cells = <2>; ranges; spmi_bus0: spmi@c42d000 { reg = <0 0x0c42d000 0 0x4000>, <0 0x0c4c0000 0 0x10000>; reg-names = "cnfg", "intr"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <0>; }; }; }; |