Based on kernel version 6.11
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sdctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Socionext UniPhier SD interface logic maintainers: - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> description: |+ SD interface logic implemented on Socionext UniPhier SoCs is attached outside SDHC, and has some SD related functions such as clock control, reset control, mode switch, and so on. properties: compatible: items: - enum: - socionext,uniphier-pro5-sdctrl - socionext,uniphier-pxs2-sdctrl - socionext,uniphier-ld11-sdctrl - socionext,uniphier-ld20-sdctrl - socionext,uniphier-pxs3-sdctrl - socionext,uniphier-nx1-sdctrl - const: simple-mfd - const: syscon reg: maxItems: 1 clock-controller: $ref: /schemas/clock/socionext,uniphier-clock.yaml# reset-controller: $ref: /schemas/reset/socionext,uniphier-reset.yaml# required: - compatible - reg additionalProperties: false examples: - | syscon@59810000 { compatible = "socionext,uniphier-ld20-sdctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x400>; clock-controller { compatible = "socionext,uniphier-ld20-sd-clock"; #clock-cells = <1>; }; reset-controller { compatible = "socionext,uniphier-ld20-sd-reset"; #reset-cells = <1>; }; }; |