Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/soc/renesas/renesas,rzv2m-pwc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas RZ/V2M External Power Sequence Controller (PWC) description: |+ The PWC IP found in the RZ/V2M family of chips comes with the below capabilities - external power supply on/off sequence generation - on/off signal generation for the LPDDR4 core power supply (LPVDD) - key input signals processing - general-purpose output pins maintainers: - Fabrizio Castro <fabrizio.castro.jz@renesas.com> properties: compatible: items: - enum: - renesas,r9a09g011-pwc # RZ/V2M - renesas,r9a09g055-pwc # RZ/V2MA - const: renesas,rzv2m-pwc reg: maxItems: 1 gpio-controller: true '#gpio-cells': const: 2 renesas,rzv2m-pwc-power: description: The PWC is used to control the system power supplies. type: boolean required: - compatible - reg - gpio-controller - '#gpio-cells' additionalProperties: false examples: - | pwc: pwc@a3700000 { compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc"; reg = <0xa3700000 0x800>; gpio-controller; #gpio-cells = <2>; renesas,rzv2m-pwc-power; }; |