Documentation / devicetree / bindings / slimbus / qcom,slim.yaml


Based on kernel version 6.9. Page generated on 2024-05-14 10:02 EST.

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/slimbus/qcom,slim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SoC SLIMbus controller

maintainers:
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description:
  SLIMbus controller used when applications processor controls SLIMbus master
  component.

allOf:
  - $ref: slimbus.yaml#

properties:
  compatible:
    items:
      - enum:
          - qcom,apq8064-slim
      - const: qcom,slim

  reg:
    items:
      - description: Physical address of controller register blocks
      - description: SLEW RATE register

  reg-names:
    items:
      - const: ctrl
      - const: slew

  clocks:
    items:
      - description: Interface clock for this controller
      - description: Interrupt for controller core's BAM

  clock-names:
    items:
      - const: iface
      - const: core

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8960.h>
    #include <dt-bindings/clock/qcom,lcc-msm8960.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
    soc {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
 
        slim@28080000 {
            compatible = "qcom,apq8064-slim", "qcom,slim";
            reg = <0x28080000 0x2000>, <0x80207c 4>;
            reg-names = "ctrl", "slew";
            interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&lcc SLIMBUS_SRC>, <&lcc AUDIO_SLIMBUS_CLK>;
            clock-names = "iface", "core";
            #address-cells = <2>;
            #size-cells = <0>;
 
            audio-codec@1,0 {
                compatible = "slim217,60";
                reg = <1 0>;
            };
        };
    };