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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: CTU CAN FD Open-source IP Core description: | Open-source CAN FD IP core developed at the Czech Technical University in Prague The core sources and documentation on project page [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf Integration in Xilinx Zynq SoC based system together with OpenCores SJA1000 compatible controllers [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top Martin Jerabek dimploma thesis with integration and testing framework description [4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf maintainers: - Pavel Pisa <pisa@cmp.felk.cvut.cz> - Ondrej Ille <ondrej.ille@gmail.com> - Martin Jerabek <martin.jerabek01@gmail.com> allOf: - $ref: can-controller.yaml# properties: compatible: oneOf: - items: - const: ctu,ctucanfd-2 - const: ctu,ctucanfd - const: ctu,ctucanfd reg: maxItems: 1 interrupts: maxItems: 1 clocks: description: | phandle of reference clock (100 MHz is appropriate for FPGA implementation on Zynq-7000 system). maxItems: 1 required: - compatible - reg - interrupts - clocks additionalProperties: false examples: - | ctu_can_fd_0: can@43c30000 { compatible = "ctu,ctucanfd"; interrupts = <0 30 4>; clocks = <&clkc 15>; reg = <0x43c30000 0x10000>; }; |