Based on kernel version 6.19. Page generated on 2026-02-12 08:38 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra Security co-processor maintainers: - Svyatoslav Ryhel <clamor95@gmail.com> - Thierry Reding <thierry.reding@gmail.com> description: Tegra Security co-processor, an embedded security processor used mainly to manage the HDCP encryption and keys on the HDMI link. properties: compatible: oneOf: - enum: - nvidia,tegra114-tsec - nvidia,tegra124-tsec - nvidia,tegra210-tsec - items: - const: nvidia,tegra132-tsec - const: nvidia,tegra124-tsec reg: maxItems: 1 interrupts: maxItems: 1 clocks: maxItems: 1 resets: maxItems: 1 iommus: maxItems: 1 operating-points-v2: true power-domains: maxItems: 1 additionalProperties: false required: - compatible - reg - interrupts - clocks - resets examples: - | #include <dt-bindings/clock/tegra114-car.h> #include <dt-bindings/interrupt-controller/arm-gic.h> tsec@54500000 { compatible = "nvidia,tegra114-tsec"; reg = <0x54500000 0x00040000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_TSEC>; resets = <&tegra_car TEGRA114_CLK_TSEC>; }; |