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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI clksel clock maintainers: - Tony Lindgren <tony@atomide.com> description: | The TI CLKSEL clocks consist of consist of input clock mux bits, and in some cases also has divider, multiplier and gate bits. properties: compatible: const: ti,clksel reg: maxItems: 1 description: The CLKSEL register range '#address-cells': enum: [ 0, 1, 2 ] '#size-cells': enum: [ 0, 1, 2 ] ranges: true "#clock-cells": const: 2 description: The CLKSEL register and bit offset required: - compatible - reg - "#clock-cells" additionalProperties: type: object examples: - | clksel_gfx_fclk: clock@52c { compatible = "ti,clksel"; reg = <0x25c 0x4>; #clock-cells = <2>; }; ... |