Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Hisilicon CPU controller maintainers: - Wei Xu <xuwei5@hisilicon.com> description: | The clock registers and power registers of secondary cores are defined in CPU controller, especially in HIX5HD2 SoC. properties: compatible: items: - const: hisilicon,cpuctrl reg: maxItems: 1 "#address-cells": const: 1 "#size-cells": const: 1 ranges: true patternProperties: "^clock@[0-9a-f]+$": type: object additionalProperties: false properties: compatible: const: hisilicon,hix5hd2-clock reg: maxItems: 1 "#clock-cells": const: 1 required: - compatible - reg - "#clock-cells" required: - compatible - reg additionalProperties: type: object examples: - | cpuctrl@a22000 { compatible = "hisilicon,cpuctrl"; #address-cells = <1>; #size-cells = <1>; reg = <0x00a22000 0x2000>; ranges = <0 0x00a22000 0x2000>; clock: clock@0 { compatible = "hisilicon,hix5hd2-clock"; reg = <0 0x2000>; #clock-cells = <1>; }; }; ... |