Documentation / trace / events-msr.rst


Based on kernel version 5.15. Page generated on 2021-11-01 09:19 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
================
MSR Trace Events
================

The x86 kernel supports tracing most MSR (Model Specific Register) accesses.
To see the definition of the MSRs on Intel systems please see the SDM
at https://www.intel.com/sdm (Volume 3)

Available trace points:

/sys/kernel/debug/tracing/events/msr/

Trace MSR reads:

read_msr

  - msr: MSR number
  - val: Value written
  - failed: 1 if the access failed, otherwise 0


Trace MSR writes:

write_msr

  - msr: MSR number
  - val: Value written
  - failed: 1 if the access failed, otherwise 0


Trace RDPMC in kernel:

rdpmc

The trace data can be post processed with the postprocess/decode_msr.py script::

  cat /sys/kernel/debug/tracing/trace | decode_msr.py /usr/src/linux/include/asm/msr-index.h

to add symbolic MSR names.