Based on kernel version 2.6.37. Page generated on 2011-03-22 21:57 EST.
1 * OpenPIC and its interrupt numbers on Freescale's e500/e600 cores 2 3 The OpenPIC specification does not specify which interrupt source has to 4 become which interrupt number. This is up to the software implementation 5 of the interrupt controller. The only requirement is that every 6 interrupt source has to have an unique interrupt number / vector number. 7 To accomplish this the current implementation assigns the number zero to 8 the first source, the number one to the second source and so on until 9 all interrupt sources have their unique number. 10 Usually the assigned vector number equals the interrupt number mentioned 11 in the documentation for a given core / CPU. This is however not true 12 for the e500 cores (MPC85XX CPUs) where the documentation distinguishes 13 between internal and external interrupt sources and starts counting at 14 zero for both of them. 15 16 So what to write for external interrupt source X or internal interrupt 17 source Y into the device tree? Here is an example: 18 19 The memory map for the interrupt controller in the MPC8544[0] shows, 20 that the first interrupt source starts at 0x5_0000 (PIC Register Address 21 Map-Interrupt Source Configuration Registers). This source becomes the 22 number zero therefore: 23 External interrupt 0 = interrupt number 0 24 External interrupt 1 = interrupt number 1 25 External interrupt 2 = interrupt number 2 26 ... 27 Every interrupt number allocates 0x20 bytes register space. So to get 28 its number it is sufficient to shift the lower 16bits to right by five. 29 So for the external interrupt 10 we have: 30 0x0140 >> 5 = 10 31 32 After the external sources, the internal sources follow. The in core I2C 33 controller on the MPC8544 for instance has the internal source number 34 27. Oo obtain its interrupt number we take the lower 16bits of its memory 35 address (0x5_0560) and shift it right: 36 0x0560 >> 5 = 43 37 38 Therefore the I2C device node for the MPC8544 CPU has to have the 39 interrupt number 43 specified in the device tree. 40 41 [0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual 42 MPC8544ERM Rev. 1 10/2007