Based on kernel version 4.16.1. Page generated on 2018-04-09 11:53 EST.
1 Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU) 2 =========================================================================== 3 4 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies 5 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared 6 by all cores within a socket. Each slice is exposed as a separate uncore perf 7 PMU with device name l3cache_<socket>_<instance>. User space is responsible 8 for aggregating across slices. 9 10 The driver provides a description of its available events and configuration 11 options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs 12 the driver also exposes a "cpumask" sysfs attribute which contains a mask 13 consisting of one CPU per socket which will be used to handle all the PMU 14 events on that socket. 15 16 The hardware implements 32bit event counters and has a flat 8bit event space 17 exposed via the "event" format attribute. In addition to the 32bit physical 18 counters the driver supports virtual 64bit hardware counters by using hardware 19 counter chaining. This feature is exposed via the "lc" (long counter) format 20 flag. E.g.: 21 22 perf stat -e l3cache_0_0/read-miss,lc/ 23 24 Given that these are uncore PMUs the driver does not support sampling, therefore 25 "perf record" will not work. Per-task perf sessions are not supported.