Documentation / parisc / registers.rst


Based on kernel version 5.14. Page generated on 2021-08-31 10:40 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154
================================
Register Usage for Linux/PA-RISC
================================

[ an asterisk is used for planned usage which is currently unimplemented ]

General Registers as specified by ABI
=====================================

Control Registers
-----------------

===============================	===============================================
CR 0 (Recovery Counter)		used for ptrace
CR 1-CR 7(undefined)		unused
CR 8 (Protection ID)		per-process value*
CR 9, 12, 13 (PIDS)		unused
CR10 (CCR)			lazy FPU saving*
CR11				as specified by ABI (SAR)
CR14 (interruption vector)	initialized to fault_vector
CR15 (EIEM)			initialized to all ones*
CR16 (Interval Timer)		read for cycle count/write starts Interval Tmr
CR17-CR22			interruption parameters
CR19				Interrupt Instruction Register
CR20				Interrupt Space Register
CR21				Interrupt Offset Register
CR22				Interrupt PSW
CR23 (EIRR)			read for pending interrupts/write clears bits
CR24 (TR 0)			Kernel Space Page Directory Pointer
CR25 (TR 1)			User   Space Page Directory Pointer
CR26 (TR 2)			not used
CR27 (TR 3)			Thread descriptor pointer
CR28 (TR 4)			not used
CR29 (TR 5)			not used
CR30 (TR 6)			current / 0
CR31 (TR 7)			Temporary register, used in various places
===============================	===============================================

Space Registers (kernel mode)
-----------------------------

===============================	===============================================
SR0				temporary space register
SR4-SR7 			set to 0
SR1				temporary space register
SR2				kernel should not clobber this
SR3				used for userspace accesses (current process)
===============================	===============================================

Space Registers (user mode)
---------------------------

===============================	===============================================
SR0				temporary space register
SR1                             temporary space register
SR2                             holds space of linux gateway page
SR3                             holds user address space value while in kernel
SR4-SR7                         Defines short address space for user/kernel
===============================	===============================================


Processor Status Word
---------------------

===============================	===============================================
W (64-bit addresses)		0
E (Little-endian)		0
S (Secure Interval Timer)	0
T (Taken Branch Trap)		0
H (Higher-privilege trap)	0
L (Lower-privilege trap)	0
N (Nullify next instruction)	used by C code
X (Data memory break disable)	0
B (Taken Branch)		used by C code
C (code address translation)	1, 0 while executing real-mode code
V (divide step correction)	used by C code
M (HPMC mask)			0, 1 while executing HPMC handler*
C/B (carry/borrow bits)		used by C code
O (ordered references)		1*
F (performance monitor)		0
R (Recovery Counter trap)	0
Q (collect interruption state)	1 (0 in code directly preceding an rfi)
P (Protection Identifiers)	1*
D (Data address translation)	1, 0 while executing real-mode code
I (external interrupt mask)	used by cli()/sti() macros
===============================	===============================================

"Invisible" Registers
---------------------

===============================	===============================================
PSW default W value		0
PSW default E value		0
Shadow Registers		used by interruption handler code
TOC enable bit			1
===============================	===============================================

-------------------------------------------------------------------------

The PA-RISC architecture defines 7 registers as "shadow registers".
Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce
the state save and restore time by eliminating the need for general register
(GR) saves and restores in interruption handlers.
Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25.

-------------------------------------------------------------------------

Register usage notes, originally from John Marvin, with some additional
notes from Randolph Chung.

For the general registers:

r1,r2,r19-r26,r28,r29 & r31 can be used without saving them first. And of
course, you need to save them if you care about them, before calling
another procedure. Some of the above registers do have special meanings
that you should be aware of:

    r1:
	The addil instruction is hardwired to place its result in r1,
	so if you use that instruction be aware of that.

    r2:
	This is the return pointer. In general you don't want to
	use this, since you need the pointer to get back to your
	caller. However, it is grouped with this set of registers
	since the caller can't rely on the value being the same
	when you return, i.e. you can copy r2 to another register
	and return through that register after trashing r2, and
	that should not cause a problem for the calling routine.

    r19-r22:
	these are generally regarded as temporary registers.
	Note that in 64 bit they are arg7-arg4.

    r23-r26:
	these are arg3-arg0, i.e. you can use them if you
	don't care about the values that were passed in anymore.

    r28,r29:
	are ret0 and ret1. They are what you pass return values
	in. r28 is the primary return. When returning small structures
	r29 may also be used to pass data back to the caller.

    r30:
	stack pointer

    r31:
	the ble instruction puts the return pointer in here.


    r3-r18,r27,r30 need to be saved and restored. r3-r18 are just
    general purpose registers. r27 is the data pointer, and is
    used to make references to global variables easier. r30 is
    the stack pointer.