Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SPMI PMIC clock divider maintainers: - Bjorn Andersson <andersson@kernel.org> - Stephen Boyd <sboyd@kernel.org> description: | Qualcomm SPMI PMIC clock divider configures the clock frequency of a set of outputs on the PMIC. These clocks are typically wired through alternate functions on GPIO pins. properties: compatible: const: qcom,spmi-clkdiv reg: maxItems: 1 clocks: items: - description: Board XO source clock-names: items: - const: xo "#clock-cells": const: 1 qcom,num-clkdivs: $ref: /schemas/types.yaml#/definitions/uint32 description: Number of CLKDIV peripherals. required: - compatible - reg - clocks - clock-names - "#clock-cells" - qcom,num-clkdivs additionalProperties: false examples: - | pmic { #address-cells = <1>; #size-cells = <0>; clock-controller@5b00 { compatible = "qcom,spmi-clkdiv"; reg = <0x5b00>; clocks = <&xo_board>; clock-names = "xo"; #clock-cells = <1>; qcom,num-clkdivs = <3>; assigned-clocks = <&pm8998_clk_divs 1>, <&pm8998_clk_divs 2>, <&pm8998_clk_divs 3>; assigned-clock-rates = <9600000>, <9600000>, <9600000>; }; }; |