Based on kernel version 6.13
. Page generated on 2025-01-21 08:20 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: LPDDR channel with chip/rank topology description description: An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS, CK, etc.) that connect one or more LPDDR chips to a host system. The main purpose of this node is to overall LPDDR topology of the system, including the amount of individual LPDDR chips and the ranks per chip. maintainers: - Julius Werner <jwerner@chromium.org> properties: compatible: enum: - jedec,lpddr2-channel - jedec,lpddr3-channel - jedec,lpddr4-channel - jedec,lpddr5-channel io-width: description: The number of DQ pins in the channel. If this number is different from (a multiple of) the io-width of the LPDDR chip, that means that multiple instances of that type of chip are wired in parallel on this channel (with the channel's DQ pins split up between the different chips, and the CA, CS, etc. pins of the different chips all shorted together). This means that the total physical memory controlled by a channel is equal to the sum of the densities of each rank on the connected LPDDR chip, times the io-width of the channel divided by the io-width of the LPDDR chip. enum: - 8 - 16 - 32 - 64 - 128 "#address-cells": const: 1 "#size-cells": const: 0 patternProperties: "^rank@[0-9]+$": type: object description: Each physical LPDDR chip may have one or more ranks. Ranks are internal but fully independent sub-units of the chip. Each LPDDR bus transaction on the channel targets exactly one rank, based on the state of the CS pins. Different ranks may have different densities and timing requirements. required: - reg allOf: - if: properties: compatible: contains: const: jedec,lpddr2-channel then: patternProperties: "^rank@[0-9]+$": $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml# - if: properties: compatible: contains: const: jedec,lpddr3-channel then: patternProperties: "^rank@[0-9]+$": $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml# - if: properties: compatible: contains: const: jedec,lpddr4-channel then: patternProperties: "^rank@[0-9]+$": $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml# - if: properties: compatible: contains: const: jedec,lpddr5-channel then: patternProperties: "^rank@[0-9]+$": $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml# required: - compatible - io-width - "#address-cells" - "#size-cells" additionalProperties: false examples: - | lpddr-channel0 { #address-cells = <1>; #size-cells = <0>; compatible = "jedec,lpddr3-channel"; io-width = <32>; rank@0 { compatible = "lpddr3-ff,0100", "jedec,lpddr3"; reg = <0>; density = <8192>; io-width = <16>; revision-id = <1 0>; }; }; lpddr-channel1 { #address-cells = <1>; #size-cells = <0>; compatible = "jedec,lpddr4-channel"; io-width = <32>; rank@0 { compatible = "lpddr4-05,0301", "jedec,lpddr4"; reg = <0>; density = <4096>; io-width = <32>; revision-id = <3 1>; }; rank@1 { compatible = "lpddr4-05,0301", "jedec,lpddr4"; reg = <1>; density = <2048>; io-width = <32>; revision-id = <3 1>; }; }; |